The quest for higher functionality and higher performance is growing rapidly in a variety of types of information equipment including, but not limited to, mobile tools such as cellular phones, multimedia instruments such as game machines, personal computers or equivalents thereto. Under such circumstances, integrated circuits (referred to as LSI hereinafter) making up these apparatuses are more strictly required to offer higher performances in near feature, in terms of high integration, high-speed operability, low power and low cost.
It is the on-chip memory that attracts attention as one of the techniques for fulfilling this requirement. The on-chip memory as used herein refers to a memory device (simply called the memory hereafter) which integrates its memory part together with a logic circuit on an LSI chip. When compared to the case where the memory is designed in the form of a single separate LSI chip, it has been known that the onchip memory offers advantages which follow: improvements in LSI mount density owing to a decrease in number of chips, and high-speed/low-power operability due to data transmission on an LSI chip.
Presently main current memory cells for the onchip memory use are static random access memory (abbreviated as SRAM hereinafter) cells. In the SRAM cells, a cell which is made up of six transistors (referred to hereafter as 6T cell) is used in most cases. Other known cells include a dynamic type memory cell consisting of one transistor and one capacitor (noted as 1T1C cell hereafter). Memory cells of this type involve several types of known ones different in capacitor structure. A representative one is a memory cell that utilizes a capacitor having a 3D structure. Known examples of this are the trench type with a capacitor formed in a silicon substrate and the stack type with a capacitor separated from a substrate and formed thereover. An example of the former is recited in FIG. 7 on page 61 of “SPECTRUM” issued by the IEEE-USA, April, 1999. An example of the latter is found in the collection of draft papers of “1999 VLSI Technology Short Course” issued by IEEE-USA, page 90, FIG. 30. Additionally, as a different example from them, an exemplary 1T1C memory cell using a planar MOS capacitor is recited in FIG. 3 of U.S. Pat. No. 6,075,720.
Furthermore, cells other than the 6T and 1T1C cells are also known. For example, in JP-A-5-291534 and U.S. Pat. No. 5,357,460, a cell is described which utilizes two transistors and one or two capacitors (referred to as 2T1C cell, 2T2C cell hereinafter). In addition, JP-A-9-12070 discloses therein a ferroelectric memory device with the switchability of 1T1C and 2T2C cells.
The 6T cell is structured from transistors only so that there is an advantage that additional steps with respect to the process for fabricating logic transistors are less in number. However, the cell area is large so that the capacity of a memory mountable on one LSI chip is limited. In contrast, the 1T1C cell is less in area than the 6T cell. Especially in those cells of the stack type and the trench type using 3D structured capacitors, it is possible to realize areas of about ⅛ or less than that of 6T cell. However, this results in an increase in process steps for fabrication of 3D structured capacitors; thus, there is a disadvantage that the cost becomes higher.
In the 1T1C cell using a MOS capacitor which is one of the above-noted prior known examples, the problem as to an increase in process step is avoidable because it is possible to fabricate capacitors at the same step as that for forming logic transistors. Obviously, memory cell transistors and capacitors are laid out side by side, and the capacitor shape also is planar; thus, it is said that a highly integrated on-chip memory is realizable when compared to 6T cells, although this cell is less in integration than the stack and trench cells.
In prior art on-chip memories having more than one capacitor, these stay merely at a level of technology which simplifies the manufacturing procedure by separately performing processes of a memory unit and a logic circuit unit or by simultaneously performing any sharable processes. For example, in JP-A-11-251647, a trench capacitor is used, which is a process unique to DRAMs.
In the circumstances stated above, a first goal or issue to be attained by the present invention is to realize an on-chip memory having a capacitor which takes advantage of the CMOS process of logic circuitry to thereby provide an onchip memory which highly satisfies the conflicting requirements for process cost reduction and integration. Furthermore, a second issue is to enable achievement of a low-voltage operation with 1V or below in the above-noted onchip memory. In addition, a third issue is to realize an onchip memory suitable also for co-integration with not only digital logic circuitry but also analog circuitry. The first issue is deemed problematical even at the present time as described in the explanation of the prior art. And, the second and third issues are the ones that are expected to become important in the near future. The second and third issues will be explained below.
As well known, the supply voltage of LSIs is potentially lowered per process generation for purposes of miniaturization of circuit elements and achievement of low power operability. In logic LSIs, products of 1.5V or less have already been available in the marketplace. The quest for lower voltage is expected to further advance from now on, which in turn requires the onchip memory also to operate with 1V or lower voltages. This can be said because if the memory unit fails to offer low-voltage operability then it becomes a must to supply different voltages to the logic unit and the memory unit, resulting in incapability to further lower the power consumption of the memory unit. Unfortunately, an operation at low voltages would result in occurrence of various problems. For instance, as well known, the amount of a read signal of a 1T1C cell is proportional to the power supply voltage. Accordingly, when reducing the operating voltage, it becomes difficult to acquire the read signal amount. To avoid this, it is required to lessen the number of memory cells on a bit line to thereby reduce the bitline capacitance or, alternatively, to enlarge the size of a capacitor to thereby increase the capacitance of such capacitor. However, any one of the both results in an increase in area, which spoils the high integrability. In addition, the operation of a sense amplifier also becomes difficult. In particular, with the prior art configuration, the operation at a voltage of about 1V or less is unrealistic. Accordingly, it is an important matter in the future to achieve a highly integrated onchip memory with low-voltage operability.
Additionally, the third issue will become important in the future by taking account of the following circumstance. As known under the name of “system-on-chip,” the circuitry to be integrated on an LSI increases in scale. For example, as suggested in JP-A-11-2511647 and JP-A-2001-196561, it is no longer uncommon that analog and digital circuits are integrated together. While transistors are used in digital circuit, the analog circuit requires the use of certain circuit elements such as capacitors in addition thereto. Therefore, in the case of integrating an onchip memory of large capacity together with a large-scale digital circuit and analog circuit, various kinds of fabrication steps are added, resulting in occurrence of anxiety as to an increase in manufacturing process cost. Another anxiety lies in a decrease in performance, reliability or manufacturing yield due to the combination of different kinds of processes.